An automated photonic wafer prober, from first specification to production.

Photonic chips are tested on the wafer, before dicing, so that faulty dies are caught before the costly steps of dicing and packaging. Light has to be coupled into each device and back out through optical fibres held within microns of its input and output ports.

On edge-coupled chips those ports sit in the side walls of trenches etched into the wafer. Every die needs a fibre array lowered into its trench, aligned in position and angle, measured and moved on, thousands of times across a wafer without drifting, on a production line that runs around the clock. A few established equipment makers dominate this market.

A photonic integrated circuit routes light through waveguides on a chip. Light gets in and out through couplers: grating couplers on the surface, or edge couplers at the chip facet, which on an undiced wafer face the wall of an etched trench. The devices I characterised span the main families, from passive couplers and splitters to interferometers, ring resonators, modulators, demultiplexers and photodiodes.

Their physics decides how a measurement can go wrong:

• Mode overlap. Coupled power depends on how well the fibre’s optical mode overlaps the waveguide’s. A small misalignment, or a mismatch in mode size, changes the reading without any change in the device.
• Reflections. Facets and fibre ends form Fabry–Pérot cavities that add a wavelength ripple, easy to mistake for the device’s own response.
• Wavelength. Rings, MZIs and demultiplexers are defined by wavelength, so any offset between the laser and the power meter shifts the result.
• Temperature. Photonic devices drift with temperature, so the wafer sits on a thermal chuck.

Knowing these effects is what lets me tell a device problem from a test problem.

I started from what customers needed to measure: wafer coverage, where each device's ports sit, the coupling geometry and the measurement sequence. I turned those into specifications for each subsystem, then chose components against measurement needs, mechanical fit, software control and availability.

Motion. I selected and integrated linear-motor wafer stages and multi-axis fibre positioners, with requirements for travel, feedback, repeatability, angular adjustment and compatibility with the thermal chuck. I also investigated jitter, homing and drift after power loss.

Optics and imaging. I sized microscope objectives, tube optics and cameras from sensor dimensions and magnification, trading resolution against working distance, field of view and illumination.

Fibre arrays. I turned chip layouts into fibre-array designs: channel arrangement, pitch and approach angle. Some chips had bonded electronics in the way, so I specified recessed arrays and anti-reflection-treated facets, then refined the designs with suppliers using customer test results.

A wafer never sits exactly where the design file says it should. It's offset, rotated, slightly warped and expands with temperature. I developed the methods that find each port anyway:

• port coordinates extracted from the chip design (GDS) and mapped from each die's local frame to the wafer
• skew correction and pivot calibration, so the fibre can rotate without the probe tip moving
• optical signal search and numerical optimisation to peak the coupling
• autofocus, wafer flatness (Z) mapping and image-based XY error mapping
• fibre-to-fibre and coupling-reference calibration

The measure of a test system is whether customers trust its numbers enough to buy it and run their production on it. They did.